Impurity ion segregation precluding layer, fabrication method thereof, isolation structure for semiconductor device using the impurity ion segregation precluding layer and fabricating method thereof

ABSTRACT

The present invention relates to the impurity ion segregation precluding layer, the fabrication method thereof, the isolation structure for the semiconductor device using the segregation precluding layer and the fabrication method thereof, which are provided to prevent impurity ions from segregating into a device isolation region in a semiconductor substrate and eventually restrain decrease in a threshold voltage due to the segregation of impurity ion, particularly, boron ions in the semiconductor substrate. The isolation structure of the semiconductor device is fabricated by forming a trench in a portion of the semiconductor substrate; placing the semiconductor substrate into a high-temperature furnace; annealing the semiconductor substrate flowing a nitride gas at about 20 l/min into the furnace; and filling an insulator in the trench. Thus, an impurity ion segregation precluding film is formed on a surface of the trench at a thickness of 1-10A in the annealing process using the nitride gas, so that the decrease in the threshold voltage of the semiconductor device is restrained and thus the semiconductor device can stably operate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device, and moreparticularly to a layer for precluding segregation of impurity ionswhich prevents impurity ion permeation between a device isolation regionand a semiconductor substrate, a fabrication method thereof, anisolation structure for a semiconductor device using the segregationprecluding layer and a fabrication method thereof.

[0003] 2. Description of the Conventional Art

[0004] A LOCOS (local oxidation of silicon) structure using a LOCOSmethod has been often used as an isolation structure of a conventionalsemiconductor device, but there is limit to improvement of integrationof the semiconductor device due to generation of a bird's beaks thereof.Thus, there is a tendency to adopt an STI (shallow trench isolation) orPGI (profiled groove isolation) structure in which a trench or a grooveis formed in a semiconductor substrate as a device isolation structureand then an insulator is filled therein.

[0005]FIG. 1 is a plan diagram illustrating a cell array unit of asemiconductor device, particularly, a DRAM (dynamic random accessmemory). A semiconductor substrate 100 is divided into an active region101 and a non-active region 102 which covers the active region 101, thenon-active region 102 being called a device isolation region. The activeregion is a part where a semiconductor device, that is, a transistor isformed and in which impurity ions are implanted, thus a source 101 a anda drain 101 b are provided. The device isolation region 102 electricallyisolates the semiconductor device and has the STI or PGI structure. Agate electrode 104 is formed on the active region 101. A channel of thetransistor is formed in a portion of the semiconductor substrate wherethe active region 101 and the gate electrode 104 are overlapped.

[0006]FIG. 2A is a cross-sectional vertical view taken along the linella-lla of FIG. 1, the line horizontally crossing the active region 101in a center point of a channel width of the transistor. As showntherein, the active region 101 of the semiconductor substrate 100 iscovered by the device isolation region 102. The device isolation region102 is etched to a predetermined depth (for example, about 0.5-0.8 mm),thereby forming a trench 102 a and an insulator 102 b is filled therein.The source 101 a and the drain 101 b, as shown in FIG. 1, are providedin the semiconductor substrate 100 having a predetermined distance and agate insulating film 103 and a gate electrode 104 are formed on thesemiconductor substrate 100.

[0007] While, FIG. 2B is a cross-sectional vertical view taken along theline llb-llb of FIG. 1, the line being perpendicular to the line lla-llaof FIG. 1. As shown therein, the trench or groove 102 a is formed in thesemiconductor substrate 100 and the insulator 102 b is filled in thetrench or groove 102 a. Here, the part 102 in which the insulator isfilled corresponds to the device isolation region. The gate insulatingfilm 103 is formed on the semiconductor substrate 100 and a gateelectrode 104 is formed thereon, the gate electrode 104 being formed inthe active region 101 and extended to the upper surface of the deviceisolation region 102. 101 c is a part where impurity ions in thesemiconductor substrate segregate to the device isolation region andthus density thereof is considerably low. Also, 101 d is a center partof the channel region of the transistor.

[0008] However, the conventional semiconductor device having the STI orPGI structure, particularly the semiconductor which is an N-channeltransistor has problems as follows.

[0009] The N-channel transistor is generally formed in a p-typesemiconductor substrate or in a p-type well. Impurity ions, inparticular, boron ions in the p-type semiconductor substrate or thep-type wall have a tendency to easily segregate to the device isolationregion and accordingly the density of the impurity ions of a portionadjacent to the device isolation region, that is, a portion 101 c of thesemiconductor substrate adjacent to a sidewall of the trench 102 abecomes decreased. Accordingly, an impurity depletion layer is formed inthe semiconductor substrate along the sidewall of the trench. As aresult, in the center part 101 d of the channel region the channel ofthe transistor is normally formed above a threshold voltage inaccordance with a voltage applied to the gate electrode, but in thechannel region adjacent to the device isolation region a channel iseasily formed below the threshold voltage, so that the threshold voltagedecreases. In addition, an electrical characteristic of thesemiconductor device is unstable that, for example, a subthresholdcurrent increases and a subthreshold current curve has a hump, whichresults in the deterioration of the semiconductor device.

SUMMARY OF THE INVENTION

[0010] Accordingly, the present invention is directed to an impurity ionsegregation precluding layer, a fabrication method thereof, an isolationstructure for semiconductor device using the impurity ion segregationprecluding layer and a fabricating method thereof which obviate theproblems and disadvantages in the conventional art.

[0011] An object of the present invention is to provide an impurity ionsegregation precluding layer and a fabrication method thereof thatprevent impurity ions in a semiconductor substrate from permeating intoa device isolation region thereof.

[0012] Also, an object of the present invention is to provide anisolation structure of a semiconductor device and a fabrication methodthereof that stabilize electric characteristics of a semiconductordevice using the above impurity ion segregation precluding layer andthereby improve reliability thereof.

[0013] To achieve these and other advantages and in accordance with thepurpose of the present invention, as embodied and broadly describedherein, there is provided an impurity ion segregation precluding layerhaving a thickness of 1-10A by placing a semiconductor substrate formedof silicon in a high-temperature furnace and annealing the semiconductorsubstrate while flowing a nitride gas thereinto at at least 20l/min.

[0014] Also, to achieve the above objects of the present invention,there is provided an isolation structure of a semiconductor device,which includes a semiconductor substrate, a trench formed in apredetermined portion of the semiconductor substrate, an impurity ionsegregation precluding layer formed on a surface of the trench, and aninsulator filled in the trench, the impurity ion segregation precludinglayer being obtained by placing the semiconductor substrate into afurnace at a high temperature and annealing the semiconductor substrateflowing a nitride gas into the furnace at about 20 l/min.

[0015] Also, to achieve the above objects of the present invention,there is provided a method for fabricating an isolation structure of asemiconductor device, which includes forming a trench in a portion of asemiconductor substrate formed of silicon corresponding to a deviceisolation region, placing the semiconductor substrate into a furnace ata high temperature and annealing the semiconductor substrate flowing anitride gas into the furnace at about 20 l/min, and filling an insulatorin the trench.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are included to provide afurther understanding of the invention and are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and together with the description serve to explain theprinciples of the invention.

[0017] In the drawings:

[0018]FIG. 1 is a plan diagram of a conventional DRAM cell array unit;

[0019]FIG. 2A is a cross-sectional vertical view taken along the linella-lla of FIG. 1;

[0020]FIG. 2B is a cross-sectional vertical view taken along the linellb-llb of FIG. 1;

[0021]FIG. 3 is a cross-sectional vertical view of an isolationstructure of a semiconductor device according to the present invention;and

[0022]FIGS. 4A through 4E are cross-sectional vertical viewsillustrating a fabrication method of an isolation structure of asemiconductor device according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] Reference will now be made in detail to the preferred embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings.

[0024]FIG. 3 is a cross-sectional vertical view illustrating anisolation structure of a semiconductor device using an insulating filmaccording to the present invention.

[0025] As shown therein, a trench 301 is formed in a device isolationregion in a semiconductor substrate 300 and an impurity ion segregationprecluding layer 302 is formed on a surface of the semiconductorsubstrate 300 along a sidewall and a bottom of the trench 301, theimpurity ion segregation precluding layer 302 having a thickness ofabout 1-9A. An insulator 303 which is a silicon oxide SiO₂ or siliconnitride Si₃N₄ is filled in the trench 301. The impurity ion segregationprecluding layer 302 at the thickness of 1-9A formed along the sidewalland bottom of the trench 301 prevents the impurity ions in thesemiconductor substrate 300 from permeating through the insulator 303 inthe trench 301, thus preventing decrease in the impurity density of thesemiconductor substrate. Accordingly, decrease in the threshold voltagein which a channel is formed below the threshold voltage is preventedand thus the reliability of the semiconductor device can improve.

[0026] The impurity ion segregation precluding layer 302 is obtained byputting the semiconductor substrate 300 having trench 301 in ahigh-temperature furnace (a furnace that is generally used in asemiconductor mass-production line) at about 800□C and annealing thesemiconductor substrate 300 while flowing nitride gas into the furnaceat over 20 l/min. Since the semiconductor substrate 300 is silicon andthe annealing process is applied with flowing the nitride gas, theimpurity ion segregation precluding layer 302 formed on the bottom andsidewall of the trench 301 of the semiconductor substrate 300 is asilicon nitride which includes silicon and nitride atoms, respectively.In the silicon nitride, it is considered that a combination ratio ofsilicon to nitride is under 0.75 because of the large inflow of thenitride gas. That is, the silicon nitride has the most stable conditionwhen three (3) silicon atoms are combined with four (4) nitride atomssuch as Si₃N₄. However, according to the present invention, it isconsidered that the combination ratio of the silicon to the nitride isnot 3:4, but the ratio of the nitride atom is higher than the silicon.Accordingly, the silicon nitride according to the present invention willbe referred to a nitrogen-rich silicon nitride. However, such anitrogen-rich silicon nitride can be Si₃N_(4.1), Si₃N_(4.2), Si₃N_(4.3),Si₃N_(4.4) . . . , or Si_(2.9)N₄, Si_(2.8)N₄, Si_(2.7)N₄, Si_(2.6)N₄,that is, when the silicon atom is 3, the nitride atom is at least 4, orwhen the nitride atom is 4, the silicon atom is less than 3. Also, theimpurity ion segregation precluding layer is considerably thin, of whicha thickness is less than 10A. Since the thickness of the insulating filmis less than 10A, the insulating film is a single nitride atom layer.However, it has been observed through the experiment that the impurityion segregation effect of this thin layer is excellent.

[0027] The thickness of the impurity ion segregation precluding layeraccording to the present invention is not a measured value but anestimated one, because “Telcor” of Telcor which the inventor used formeasuring the film can only measure a film which has a thickness of atleast 10A. As a result of measuring the thickness of the impurity ionsegregation precluding layer, it indicated 10A, which is the lowestvalue that the instrument could measure. Thus, it is estimated that thethickness of the film is 10A or less.

[0028] The reason that it is considered that the film exists, althoughthe thickness of the film was not accurately measured by the instrumentis as follows.

[0029] First, as described above, when forming the device isolationregion by filling the insulator in the trench and then forming thetransistor on the semiconductor substrate, after annealing thesemiconductor substrate with the inflow the nitride gas at at least 20l/min, decrease in the threshold voltage due to the impurity ionsegregation of the semiconductor substrate was not shown. Accordingly,it can be assumed that there exists in the device isolation region afilm that prevents the impurity permeation between the insulator and thesemiconductor substrate.

[0030] Further, the following explains the reason why it is assumed thatthe impurity permeation preventing film is a silicon nitride.

[0031] After performing the annealing using the nitride gas, theinventor etched the semiconductor substrate with a BOE (buffered oxideetchant=buffered hydrofluorine), formed the device isolation region byfilling the insulator in the trench and fabricated a transistor usingthe semiconductor substrate. Then, such a transistor had the same resultas the semiconductor substrate before performing the BOE etching.Accordingly, it is estimated that the impurity permeation preventingfilm is not the silicon oxide, but there is provided a material of whichnitride and silicon are combined, that is, the silicon nitride, sincethe silicon substrate was annealed using the nitride gas. Further, sincethe amount of the employed nitride gas is considerably larger than thenitride gas (6 l/min at its maximum), which is used for the annealingprocess in the semiconductor device fabrication process, it isconsidered to be the nitrogen-rich silicon nitride.

[0032] While, the inventor additionally carried out the followingexperiment to evaluate the existence of the impurity ion segregationprecluding layer and the characteristics thereof.

[0033] Table 1 illustrates results of the experiment that measured athickness of an oxide formed on the semiconductor substrate when thesemiconductor substrate was placed in the furnace at a temperature of atleast about 800□C and annealed in an oxygen atmosphere while flowing thenitride gas at 12 l/min and 20 l/min, respectively, thereinto. When thenitride gas was not flowed thereinto, the thickness of the oxide formedon the silicon substrate which was obtained under the same conditions inthe oxygen atmosphere was 70A. However, when the nitride gas was flowedinto the furnace at 12 l/min and 20 l/min, respectively, and annealed inthe oxygen atmosphere, the thickness of each oxide formed on thesemiconductor substrate was less than 70A. In other words, when theannealing process was performed in the oxygen atmosphere with the inflowof the nitride gas into the furnace at 12 l/min, the oxide formed on thesilicon semiconductor substrate had a thickness of 66.8A on averagethrough experiments of three times, which had nearly the same result asthe oxide formed on the semiconductor substrate without the nitride gasinflow into the furnace. Further, when the annealing process wasperformed in the oxygen atmosphere with the inflow of the nitride gasinto the furnace at 20 l/min, the oxide formed on the siliconsemiconductor substrate had a thickness of 36.6A on average throughexperiments of three times, which has about half the thickness of theoxide formed on the semiconductor substrate without the nitride gasinflow into the furnace. Accordingly, it can be seen that when thenitride gas was flowed at least at 20 l/min during the annealingprocess, there is formed a film that prevents oxidization of a surfaceof the silicon semiconductor substrate.

[0034] Generally, it is known that an oxide is hardly formed on Si₃N₄,which is a stable silicon nitride. Thus, it can be assumed that growthof the oxide was restrained because there was formed the silicon nitrideof which the nitride and the silicon were combined. In particular, theoxide grows, but the growth speed of the oxide was controlled whilegrowing. Thus, it is considered that the silicon nitride has an unstablecombination of a compound, not a stable one, and thus the inventorreferred to the silicon nitride as the nitrogen-rich silicon nitride.

[0035] Further, as a result of the experiments, the oxide, formed on thesemiconductor substrate when the nitride gas was flowed into the furnaceat 12 l/min, has the thickness similar to the oxide which was formedwithout flowing the nitride gas into the furnace. Thus, it can beassumed that when the nitride gas is flowed at 12 l/min, thenitrogen-rich silicon nitride is not sufficiently formed on thesemiconductor substrate, but when the annealing process is performedwith the inflow of the nitride gas into the furnace at at least 20l/min, there is formed on the surface of the trench the nitrogen-richsilicon nitride that has a desirable effect of precluding the impurityion segregation. However, considering the fabrication cost, it ispreferred to perform the annealing process with the inflow of thenitride gas into the furnace at 20 to 50 l/min. TABLE 1 Experiment(time) 1 2 3 average Nitride 12 thickness of 66.9 66.5 67.0 66.8 (l) 20oxide(A) 39.3 31.2 39.3 36.6

[0036] Next, a fabrication method of the semiconductor device isolationstructure of FIG. 3 according to the present invention will be describedwith the reference to FIGS. 4A to 4E.

[0037] First, as shown in FIG. 4A, a trench 401 is formed in a part of asemiconductor substrate 400 corresponding to a device isolation region.The trench 401 is formed by the following process. First, a pad oxide411 is formed over the semiconductor substrate 400. The pad oxide 411can be formed by oxidizing a silicon substrate by a thermal oxidizationmethod or deposited by a chemical vapor deposition method. A siliconnitride 412 is deposited on the pad oxide 411, and a photoresist film(not shown) is applied on the silicon nitride 412 and a photolithographyprocess is performed, so that the photoresist film remains on thesilicon nitride 412, which corresponds to an active region, whichbecomes a photoresist film pattern (not shown). Using the photoresistfilm pattern as a mask, the silicon nitride 412 and the pad oxide 411are etched by a reactive ion etching method and then the semiconductorsubstrate 400 formed under the etched pad oxide 411 is etched to apredetermined depth, thereby forming the trench 401. Further, to recovera surface of the semiconductor substrate 400 which has been damaged inthe etching process to form the trench 401, the semiconductor substrateis annealed at 1050□C in an O₂ atmosphere, so that there is formed athermal oxide 402 at a thickness of about 50-200A on the semiconductorsubstrate 400 in the trench 401.

[0038] As shown in FIG. 4B, the thermal oxide 402 is removed using an HFsolution.

[0039] Next, as shown in FIG. 4C, the semiconductor substrate of FIG. 4bis placed in a furnace at a temperature of at least 800□C and annealedwhile flowing a nitride gas N₂ into the furnace at 20-50 l/min, therebyforming an impurity ion segregation precluding layer 403 at a thicknessof 1-10A on the semiconductor substrate 400 along an inner wall and abottom of the trench 401. Here, the impurity ion segregation precludinglayer 403 is the nitrogen-rich silicon nitride which has been abovedescribed. Also, ia nitride ion implantation method can be performed asa method for forming the nitrogen-rich silicon nitride on thesemiconductor substrate, however since such an ion implantation methoddamages the surface of the semiconductor substrate it is notrecommendable. Specifically, when a portion of the semiconductorsubstrate adjacent to the device isolation region is damaged, a leakagecurrent may be generated, thus it is more desirable to perform theannealing process in the nitride atmosphere, rather than the ionimplantation method.

[0040] As shown in FIG. 4D, an insulator 404 is formed on an entiresurface of the resultant structure of FIG. 4C including the trench 401and an annealing process is performed to the resultant structure. Here,the insulator is preferably a silicon oxide or silicon nitride. Then, achemical mechanical polishing process is performed to the insulator 404for thereby removing a portion of the insulator formed on the siliconnitride 412, so that a surface level of the resultant semiconductorsubstrate 400 becomes planarized.

[0041] Next, as shown in FIG. 4E, the silicon nitride 412 and the padoxide 411 are sequentially removed, thereby completing the fabricationof the isolation structure of the semiconductor device.

[0042] As described above, the thin impurity ion segregation precludinglayer, that is, the nitrogen-rich silicon nitride at a thickness ofseveral A is formed on the surface of the part of the semiconductorsubstrate corresponding to the device isolation region, therebypreventing the inter-permeation of the impurity ions between the deviceisolation reclion and the semiconductor substrate, which has an effectof improving the reliability of semiconductor device by stabilizing theelectric characteristics of the device.

[0043] It will be apparent to those skilled in the art that variousmodifications and variations can be made in the impurity ion segregationprecluding layer, the fabrication method thereof, the isolationstructure for the semiconductor device using the segregation precludinglayer and the fabrication method thereof of the present inventionwithout departing from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. An impurity ion segregation precluding layerformed on a silicon substrate and having a thickness of 10A or less,said segregation precluding layer being obtained by placing the siliconsubstrate in a high-temperature furnace and annealing the siliconsubstrate while flowing a nitride gas at at least 20 l/min thereinto. 2.The impurity ion segregation precluding layer according to claim 1,wherein the impurity ion segregation precluding layer is a nitrogen-richsilicon nitride.
 3. The impurity ion segregation precluding layeraccording to claim 1, wherein the annealing process is performed in thefurnace at about 800□C.
 4. The impurity ion segregation precluding layeraccording to claim 1, wherein the impurity ion segregation precludinglayer restrains oxidization of the silicon substrate.
 5. The impurityion segregation precluding layer according to claim 1, wherein theimpurity ion segregation precluding layer is not etched by a bufferedoxide etchant (BOE).
 6. A method for fabricating an impurity ionsegregation precluding layer, comprising the steps of: preparing asilicon substrate and placing the silicon substrate into a furnace at ahigh temperature and annealing the silicon substrate flowing a nitridegas at about 20 l/min into the furnace.
 7. The method according to claim6, wherein the annealing process is performed in the furnace at about800□C.
 8. The method according to claim 6, wherein the annealing processis performed to form a nitrogen-rich silicon nitride having a thicknessof 10 A or less.
 9. An isolation structure of a semiconductor device,comprising: a semiconductor substrate; a trench formed in apredetermined portion of the semiconductor substrate; an impurity ionsegregation precluding layer formed on a surface of the trench; and aninsulator filled in the trench, the impurity ion segregation precludinglayer being obtained by placing the semiconductor substrate into afurnace at a high temperature and annealing the semiconductor substrateflowing a nitride gas at about 20 l/min into the furnace.
 10. Theisolation structure according to claim 9, wherein the impurity ionsegregation precluding layer has a thickness of 10A or less.
 11. Theisolation structure according to claim 9, wherein the insulator is asilicon oxide or a silicon nitride.
 12. The isolation structureaccording to claim 9, wherein the impurity ion segregation precludinglayer is a nitrogen-rich silicon nitride.
 13. A method of fabricating anisolation structure of a semiconductor device, comprising the steps of:preparing a semiconductor substrate; forming a trench in a portion ofthe semiconductor substrate corresponding to a device isolation region;forming a nitrogen-rich silicon nitride having a thickness of 10A orless on a surface of the trench; and filling an insulator in the trench.14. A method of fabricating an isolation structure of a semiconductordevice, comprising the steps of: preparing a semiconductor substrate;forming a trench in a portion of the semiconductor substratecorresponding to a device isolation region; placing the semiconductorsubstrate into a furnace at a high temperature; annealing thesemiconductor substrate flowing a nitride gas at about 20 l/min into thefurnace; and filling an insulator in the trench.
 15. The methodaccording to claim 14, wherein the annealing process is performed toform an impurity ion segregation precluding layer having a thickness of10A or less on a sidewall and a bottom surface of the trench of thesemiconductor substrate.
 16. The method according to claim 15, whereinthe impurity ion segregation precluding layer is a nitrogen-rich siliconnitride.
 17. The method according to claim 14, further comprising thesteps of: after forming the trench, annealing the semiconductorsubstrate at a temperature of 1000-1050□C in an oxygen atmosphere, forthereby forming a thermal oxide on the surface of the trench, thethermal oxide having a thickness of 50-200A; and removing the thermaloxide with an HF solution.
 18. The method according to claim 14, whereinthe step of filling the insulator in the trench includes: forming aninsulating film over an entire surface of the semiconductor substratewhich is obtained from the annealing process; and planarizing theinsulating film by a chemical mechanical polishing method, so that theinsulating film only remains in the trench.
 19. The method according toclaim 14, wherein the step of forming the trench includes: forming a padoxide on the semiconductor substrate; forming a silicon nitride on thepad oxide; forming a photoresist pattern on a portion of the siliconnitride corresponding to an active region; and removing the siliconnitride and the pad oxide by using the photoresist pattern as a mask andetching the semiconductor substrate formed under the removed pad oxideto a predetermined depth.